View THCV216_8853301.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. thcv215 and THCV216 v- by -one ? hs high-speed video data transmitter and receiver general description thcv215 and THCV216 are designed to support video data transmission between the host and d isplay. the chipset can transmit 39bit video data and 3bit sync data via only a single differential cable at an lvds clock frequency from 20mhz to 100mhz. the chipset, which has two high-speed data lanes, can transmit the video data up to 1080p/10b/60hz, 1080p/12b/60hz. the m ax imum serial data rate is 3.75gbps/lane. color depth link lvds clock frequency 6bit single/dual 20mhz to 100mhz 8bit single/dual 20mhz to 100mhz 10bit single/dual 20mhz to 85mhz 12bit single/dual 20mhz to 75mhz features ? color depth selectable: 6/8/10/12 bit ? single/dual link selectable ? ac coupling ? lvds input internal termination ? core 1.8v, lvds 3.3v ? package: 64 pin tssop ? wide frequency range ? cdr requires no external frequency reference ? supports spread spectrum clocking: up to 30 khz/ ? 0. 5%(center spread) ? v- by -one ? hs standard v er sion1.4 compliant block diagram tla0+/- ? ? ? tlf0+/- tlclk0+/- tla1+/- ? ? ? tlf1+/- tlclk1+/- color depth (6/8/10/12) single/dual pre-emphasis pdn lvds deserializer lvds deserializer formatter serializer serializer pll ? ? ? ? ? ? controls htpdn lockn color depth (6/8/10/12) single/dual rs pdn deserializer deserializer cdr deskew & formatter pll lvds serializer lvds serializer controls thcv215 THCV216 rla0+/- ? ? ? rlf0+/- rlclk0+/- rla1+/- ? ? ? rlf1+/- rlclk1+/- ? ? ? ? ? ? tx0+ tx0- rx0+ rx0- tx1+ tx1- rx1+ rx1- 1/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. contents page general description ................................................................................................................................................. 1 features .................................................................................................................................................................... 1 block diagram ......................................................................................................................................................... 1 pin diagram ............................................................................................................................................................. 3 pin description ......................................................................................................................................................... 4 functional description ............................................................................................................................................ 5 absolute maximum ratings0f ............................................................................................................................. 13 operating conditions ............................................................................................................................................ 13 electrical specifications ........................................................................................................................................ 14 ac timing diagrams and test circuits ............................................................................................................... 17 package ................................................................................................................................................................... 24 notices and requests ................................................................................................................................ ............. 25 2/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. pin diagram lagnd 1 64 lpvdl lpvdh 1 64 lagnd lavdh 2 63 lpgnd lpgnd 2 63 lavdh tla0- 3 62 sdsel sdsel 3 62 rla0- tla0+ 4 61 col1 col1 4 61 rla0+ tlb0- 5 60 col0 col0 5 60 rlb0- tlb0+ 6 59 rdy htpdn 6 59 rlb0+ tlc0- 7 58 pdn lockn 7 58 rlc0- tlc0+ 8 57 htpdn vdl 8 57 rlc0+ tlclk0- 9 56 lockn gnd 9 56 rlclk0- tlclk0+ 10 55 vdl cpvdl0 10 55 rlclk0+ tld0- 11 54 gnd cpgnd0 11 54 rld0- tld0+ 12 53 cavdl cavdl 12 53 rld0+ tle0- 13 52 cagnd cagnd 13 52 rle0- tle0+ 14 51 tx0- rx0- 14 51 rle0+ tlf0- 15 50 tx0+ rx0+ 15 50 rlf0- tlf0+ 16 49 cagnd cagnd 16 49 rlf0+ tla1- 17 48 tx1- cagnd 17 48 rla1- tla1+ 18 47 tx1+ rx1- 18 47 rla1+ tlb1- 19 46 cagnd rx1+ 19 46 rlb1- tlb1+ 20 45 cavdl cagnd 20 45 rlb1+ tlc1- 21 44 cpgnd cavdl 21 44 rlc1- tlc1+ 22 43 cpvdl cpgnd1 22 43 rlc1+ tlclk1- 23 42 drv1 cpvdl1 23 42 rlclk1- tlclk1+ 24 41 drv0 gnd 24 41 rlclk1+ tld1- 25 40 pre1 vdl 25 40 rld1- tld1+ 26 39 pre0 reserved1 26 39 rld1+ tle1- 27 38 reserved0 pdn 27 38 rle1- tle1+ 28 37 reserved1 reserved2 28 37 rle1+ tlf1- 29 36 gnd reserved3 29 36 rlf1- tlf1+ 30 35 vdl rs 30 35 rlf1+ lavdh 31 34 lpgnd lpgnd 31 34 lavdh lagnd 32 33 lpvdl lpvdh 32 33 lagnd THCV216 64pin tssop thcv215 64pin tssop 3/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. pin description thcv215 THCV216 pin name pin # type* description pin name pin # type* description tx0 +/- 50,51 co rx0 +/- 15,14 ci tx1 +/- 47,48 co rx1 +/- 19,18 ci tla0+/- 4,3 li rla0+/- 61,62 lo tlb0+/- 6,5 li rlb0+/- 59,60 lo tlc0+/- 8,7 li rlc0+/- 57,58 lo tlclk0+/- 10,9 li rlclk0+/ 55,56 lo tld0+/- 12,11 li rld0+/- 53,54 lo tle0+/- 14,13 li rle0+/- 51,52 lo tlf0+/- 16,15 li rlf0+/- 49,50 lo tla1+/- 18,17 li rla1+/- 47,48 lo tlb1+/- 20,19 li rlb1+/- 45,46 lo tlc1+/- 22,21 li rlc1+/- 43,44 lo tlclk1+/- 24,23 li rlclk1+/ 41,42 lo tld1+/- 26,25 li rld1+/- 39,40 lo tle1+/- 28,27 li rle1+/- 37,38 lo tlf1+/- 30,29 li rlf1+/- 35,36 lo lockn 56 i lock detect input lockn 7 o lock detect output (open drain) htpdn 57 i hot plug detect input htpdn 6 o hot plug detect output (open drain) pdn 58 i power down input h: normal operation l: power down (cml output high fix, other high-z) pdn 27 i power down input h: normal operation l: power down (high-z) col1, col0 61,60 i color depth select input l,l: 6bit l,h: 8bit h,l: 10bit h,h: 12bit col1, col0 4,5 i color depth select input l,l: 6bit l,h: 8bit h,l: 10bit h,h: 12bit sdsel 62 i single/dual select input l: channel0 enable, channel1 disable h: channel0, channel1 enable sdsel 3 i single/dual select input l: channel0 enable, channel1 disable h: channel0, channel1 enable drv1 42 i must be tied to gnd drv0 41 i must be tied to vdl pre1, pre0 40,39 i pre-emphasis level select input l,l: 0% h,l: 100% l,h: not available h,h: not available rdy 59 o link status ready output l: not ready h: ready reserved 1,2 26,28 i must be tied to gnd reserved1 37 i field bet mode enable input l: normal operation (default) h: field bet mode enabled reserved3 29 i field bet mode enable input l: normal operation (default) h: field bet mode enabled reserved0 38 i must be tied to gnd vdl 8,25 p 1.8v power supply pin for digital circuitry gnd 9,24 p ground pin for digital circuitry cavdl 12,21 p 1.8v power supply pin for cml input gnd 36,54 p ground pin for digital circuitry cagnd 13,16, 17,20 p ground pin for cml input cavdl 45,53 p 1.8v power supply pin for cml output cpvdl0 10 p 1.8v power supply pin for pll circuitry cagnd 46,49,52 p ground pin for cml output cpgnd0 11 p ground pin for pll circuitry cpvdl 43 p 1.8v power supply pin for pll circuitry cpvdl1 23 p 1.8v power supply pin for pll circuitry cpgnd 44 p ground pin for pll circuitry cpgnd1 22 p ground pin for pll circuitry lpvdl 33,64 p 1.8v power supply pin for lvds pll lpvdh 1,32 p 3.3v power supply pin for lvds pll lpgnd 34,63 p ground pin for lvds pll circuitry lpgnd 2,31 p ground pin for lvds pll circuitry lavdh 2,31 p 3.3v power supply pin for lvds input lavdh 34,63 p 3.3v power supply pin for lvds output lagnd 1,32 p ground pin for lvds input lagnd 33,64 p ground pin for lvds output *type symbol note) all cmos inputs are 1.8v-inputs i=1.8v cmos input, o=1.8v cmos output, io3=3.3v cmos i/o except for THCV216's rs li=lvds input, lo= lvds output ci=cml input, co=cml output p=power vdl 35,55 p 1.8v power supply pin for digital circuitry rs 30 io3 direction of rs pin depends on reserved3. lvds swing range select input when reserved3=l h: normal swing (350mv typ.) l: reduced swing (200mv typ.) field bet output when reserved3=h. goes low when errors detected. cml data input lvds data output lvds data input cml data output 4/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. functional description functional overview with v- by -one ? hs s proprietary encoding scheme and cdr (clock and data recovery) architecture, thcv215 and THCV216 enable transmission of 18/24 /30/36bits per pixel video data (rn/gn/bn/contn), hsync (hsyncn), vsync (vsyncn) data and data enable (de) by single/dual differential pair cable with minimal external components. thcv215, the transmitter, inputs lvds data (including video data, hsync, vsync and de) and serializes video data and hsync, vsync data separately, depending on the polarity of de . de is a signal which indicates whether video or hsync, vsync data are active. when de is high, it serializes video dat a inputs into a single differential data stream. and it transmits serialized hsync, vsync data when de is low. THCV216, the receiver, automatically extracts the clock from the incoming data stream and converts the serial data into video data with de being high or hsync, vsync data with de being low, recognizing which type of serial data is being sent by the transmitter. and it outputs the recovered data in the form of lvds data. THCV216 can seamlessly operate for a wide range of a serial bit rate from 600mbps to 3.75gbps/channel , detecting the frequency of an incoming data stream, and recovering both the clock and data by itself. it does not need any external frequency reference, such as a crystal oscillator. data enable requirement (de) there are some requirements for de as described in figure 2 , figure 3 and table 15 . dual lvds input to thcv215 should be synchronized in terms of de transition. see figure 2 . if de=low, hsync and vsync data of same cycle are transmitted. otherwise video data of that are transmitted (de=high). sync data from receiver in de=high period are previous data of de transition. see figure 3 . the length of de being low and high is at least 2 clock cycles long as described in table 15 . data enable must be toggled like high -> low -> high at regular interval. figure 1. conceptual diagram of the basic operation of the chipset figure 2. service condition of de input synchronization h l de thcv 216 thcv 215 de d[39:0] hsync vsync rn/gn/bn contn hsyncn vsyncn h l d[39:0] hsync vsync rn/gn/bn contn hsyncn vsyncn vdiff = (tlclk0+) C (tlclk0-) vdiff = (tlclk1+) C (tlclk1-) vdiff = (tlc0+) C (tlc0-) vdiff = (tlc1+) C (tlc1-) de de de de de de de de de de de de 5/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. figure 3. video and sync data transmission timing diagram single/dual link mode function (sdsel) sdsel mode function h single channel 0 active and channel 1 power down l dual both channel 0 and channel 1 active table 1. single/dual mode select color depth mode function (col [1:0]) col[1:0] color depth lvds clock frequency range l,l 6bit 20mhz to 100mhz l,h 8b it 20mhz to 100mhz h,l 10b it 20mhz to 85 mhz h,h 12b it 20mhz to 75mhz table 2. color depth mode select de vsyncn hsyncn rn/gn/bn contn tdeh tdel 1 cycle valid data valid data low low valid data low high keep the last data of de=l period THCV216 output low de vsync hsync rn/gn/bn contn tdeh tdel 1 cycle valid data valid data invalid invalid valid data low high invalid thcv215 input low n=0,1 n=0,1 6/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. lvds mapping lvds data (video data, hsync, vsync, de) are mapped as figure 4 . tlc0[6] is special bit for de(data enable), and tlc0[5:4] are for hsync, vsync data bits and the other bits are for video data. the number of lvds channel depends on color depth mode(col[1:0]). if sdsel=low, only channel 0 ( figure 4 , n=0) is active. if sdsel=high, both channel 0/1( figure 4 , n=0/1) are active. (tlc1[6:4] are not available). depending on color mode, tld1[6] and tld0[6] are not available. see table 3 . figure 4. lvds mapping timing diagram tlan6 vdiff = (tlclkn +) - (tlclkn-) n=0,1 tlan5 tlan4 tlan3 tlan2 tlan1 tlan0 tlan6 tlan5 tlan4 tlan3 tlan2 tlan1 ttcip vdiff=0v next cycle current cycle tlan1 tlan0 previous cycle tlbn6 tlbn5 tlbn4 tlbn3 tlbn2 tlbn1 tlbn0 tlbn6 tlbn5 tlbn4 tlbn3 tlbn2 tlbn1 tlbn1 tlbn0 tlcn6 (de) tlcn5 (v) tlcn4 (h) tlcn3 tlcn2 tlcn1 tlcn0 tlcn3 tlcn2 tlcn1 tlcn1 tlcn0 tldn6 tldn5 tldn4 tldn3 tldn2 tldn1 tldn0 tldn6 tldn5 tldn4 tldn3 tldn2 tldn1 tldn1 tldn0 tlen6 tlen5 tlen4 tlen3 tlen2 tlen1 tlen0 tlen6 tlen5 tlen4 tlen3 tlen2 tlen1 tlen1 tlen0 tlfn6 tlfn5 tlfn4 tlfn3 tlfn2 tlfn1 tlfn0 tlfn6 tlfn5 tlfn4 tlfn3 tlfn2 tlfn1 tlfn1 tlfn0 tlan +/- tlbn +/- tlcn +/- tldn +/- tlen +/- tlfn +/- control data bit data enable tlcn6 (de) tlcn5 (v) tlcn4 (h) color depth 12,10, 8, 6 7/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. table 3. lvds mapping table l,l (6bit) l,h (8bit) h,l (10bit) h,h (12bit) tlan[0] rlan[0] rn[0] rn[2] rn[4] rn[6] d2 tlan[1] rlan[1] rn[1] rn[3] rn[5] rn[7] d3 tlan[2] rlan[2] rn[2] rn[4] rn[6] rn[8] d4 tlan[3] rlan[3] rn[3] rn[5] rn[7] rn[9] d5 tlan[4] rlan[4] rn[4] rn[6] rn[8] rn[10] d6 tlan[5] rlan[5] rn[5] rn[7] rn[9] rn[11] d7 tlan[6] rlan[6] gn[0] gn[2] gn[4] gn[6] d10 tlbn[0] rlbn[0] gn[1] gn[3] gn[5] gn[7] d11 tlbn[1] rlbn[1] gn[2] gn[4] gn[6] gn[8] d12 tlbn[2] rlbn[2] gn[3] gn[5] gn[7] gn[9] d13 tlbn[3] rlbn[3] gn[4] gn[6] gn[8] gn[10] d14 tlbn[4] rlbn[4] gn[5] gn[7] gn[9] gn[11] d15 tlbn[5] rlbn[5] bn[0] bn[2] bn[4] bn[6] d18 tlbn[6] rlbn[6] bn[1] bn[3] bn[5] bn[7] d19 tlcn[0] rlcn[0] bn[2] bn[4] bn[6] bn[8] d20 tlcn[1] rlcn[1] bn[3] bn[5] bn[7] bn[9] d21 tlcn[2] rlcn[2] bn[4] bn[6] bn[8] bn[10] d22 tlcn[3] rlcn[3] bn[5] bn[7] bn[9] bn[11] d23 tlcn[4] rlcn[4] hsyncn hsyncn hsyncn hsyncn hsync tlcn[5] rlcn[5] vsyncn vsyncn vsyncn vsyncn vsync tlcn[6] rlcn[6] den(*2) den(*2) den(*2) den(*2) de tldn[0] rldn[0] rn[0] rn[2] rn[4] d0 tldn[1] rldn[1] rn[1] rn[3] rn[5] d1 tldn[2] rldn[2] gn[0] gn[2] gn[4] d8 tldn[3] rldn[3] gn[1] gn[3] gn[5] d9 tldn[4] rldn[4] bn[0] bn[2] bn[4] d16 tldn[5] rldn[5] bn[1] bn[3] bn[5] d17 tldn[6] rldn[6] n/a(*1) contn[1] contn[3] d25(*3) tlen[0] rlen[0] rn[0] rn[2] d30 tlen[1] rlen[1] rn[1] rn[3] d31 tlen[2] rlen[2] gn[0] gn[2] d28 tlen[3] rlen[3] gn[1] gn[3] d29 tlen[4] rlen[4] bn[0] bn[2] d26 tlen[5] rlen[5] bn[1] bn[3] d27 tlen[6] rlen[6] contn[2] contn[4] d24(*3) tlfn[0] rlfn[0] channel power rn[0] d38 tlfn[1] rlfn[1] rn[1] d39 tlfn[2] rlfn[2] gn[0] d36 tlfn[3] rlfn[3] gn[1] d37 tlfn[4] rlfn[4] bn[0] d34 tlfn[5] rlfn[5] bn[1] d35 tlfn[6] rlfn[6] contn[1] d33 n=0,1 : if sdsel=l, channel 1(n=1) is power down *1 n/a: not available, THCV216 output rldn[6]=low. *2 de must be same polarity(tlc0[6] = tlc1[6]) when sdsel=h *3 3d information flags defined in the v-by-one ? hs standard are assigned to the following bit. v-by-one ? hs standard packer/unpacker d[24](3dlr) <=> lvds t/rlen[6] v-by-one ? hs standard packer/unpacker d[25](3den) <=> lvds t/rldn[6] symbol defined by v-by-one ? hs thcv215 input THCV216 output color depth (col[1:0]) symbol defined by v-by-one ? hs channel power down channel power down channel power down channel power down channel power down 8/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)20 1 6 thine electronics, inc. cml buffer figure 5. cml buffer scheme lock detect and hot-plug function lockn and htpdn are both open drain output from THCV216. pull-up resistors are needed at thcv215 side to vdl. see figure 6 . if THCV216 is not active (power down mode (pdn=l) or powered off), htpdn is open. otherwise, htpdn is pull ed down by THCV216. htpdn of thcv215 side is high when THCV216 is not active or the receiver board is not connected. then thcv215 enters into the power down mode. when htpdn transits from high to low, thcv215 starts up and transmits training pattern for link training. lockn indicates whether THCV216 is in the lock state or not. if THCV216 is in the unlock state, lockn is open. otherwise (in the lock state), its pull ed down by THCV216. thcv215 keeps transmitting training pattern until lockn transits to low. after training done, THCV216 sinks current and lockn is low. then thcv215 starts transmitting normal video pattern. figure 6. hot-plug and lock detect scheme cavdl txn + rxn + txn - rxn - vterm ~ 1.3v c=75 200nf 50? n=0,1 cavdl cagnd thcv215 THCV216 cml transmitter cml receiver 50? c=75 200nf 50? 50? zdiff=100? vdl (thcv215 side) vdl (thcv215 side) htpdn lockn 10k thcv215 THCV216 10k 9/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. no htpdn connection option htpdn connection between thcv215 and THCV216 can be omitted as an application option. in this case, htpdn at the transmitter side should always be taken ad low. see figure 7 . figure 7. htpdn is not connected scheme vdl (thcv215 side) htpdn lockn 10k thcv215 THCV216 htpdn 10/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. thcv215 pre-emphasis function (pre [1:0]) pre-emphasis can equalize severe signal degradation caused by long distance or high-speed transmission. two pins, pre1 and pre0, select the strength of pre-emphasis. see table 4 . pre[1:0] d escription l,l w/o pre - emphasis h,l w/ 100% pre - emphasis l,h / h,h not available table 4. pre-emphasis function table thcv215 power down function (pdn) by setting the pdn pin to low, it results in the power down mode. all the internal circuitry turns off and the both tx n +/ - (n=0, 1) outputs turn to vdl. THCV216 power down function (pdn) by setting the pdn pin to low, it results in the power down mode. all the internal circuitry turns off and the rlxn+/- (x=a, b, c, d, e, f, clk, n=0, 1) outputs turn to high- z. thcv215 link ready function (rdy) this is a cmos output for indicating the link status. rdy=high if link is ready. 11/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. field bet operation in order to help users to check the validity of high speed serial links (cml lines), thcv215/THCV216 have an operation mode in which they act as the bit error tester (bet). in this mode, thcv215 internally generates a test pattern, which is then serialized onto the cml high speed lines. THCV216 receives the data stream and checks the sampled data for bit errors. this "field bet" mode is activated by setting reserved1= h on thcv215 and reserved3= h on THCV216 (refer to table 5 ). in the field bet mode, the on-chip pattern generator on thcv215 is enabled and generates the test pattern as long as the lvds clocks (tlclk0+/-, tlclk1+/-) are applied. other lvds data inputs may be left open or applied with any pattern. they are ignored by thcv215. the generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the cml channels. as for THCV216, the internal test pattern check circuit gets enabled and the rs pin, which is normally an input, turns into an output for the pattern checker (lvds output level is internally configured to be "normal swing ) . the rs pin goes low whenever bit errors occur, and it stays high when there is no bit error. please refer to figure 8 . product thcv215 thc v216 pin name reserved1 reserved3 rs normal l l 3.3v input h : normal swing, l: reduced swing field bet h h 3.3v output goes low when bit errors occur. table 5. field bet operation pin settings figure 8. field bet configuration thcv215 THCV216 lvds clock to tlclk0, 1 reserved1=h (field bet mode) reserved3=h (field bet mode) test pattern checker test pattern generator lvds data inputs are ignored r s test point for field bet lvds swing select for normal operation 12/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. absolute maximum ratings 0f ? table 6. thcv215 absolute maximum ratings 7deoh 7+&9$evroxwh0d[lpxp5dwlqjv operating conditions table 8. thcv215 operating condition s table 9. THCV216 operating conditions ? absolute maximum ratings are those values beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of electrical characteristics specify conditions for device operation. parameter min. typ. max. units 1.8v supply voltage vdl,cavdl,cpvdl,lpvdl -0.3 - +2.1 v 3.3v supply voltage(lavdh) -0.3 - +4.0 v 1.8v cmos input voltage -0.3 - vdl+0.3 v 1.8v cmos output voltage -0.3 - vdl+0.3 v lvds receiver input voltage -0.3 - lavdh+0.3 v cml transmitter output voltage -0.3 - cavdl+0.3 v output current -50 - 50 ma storage temperature -55 - +125 c junction temperature - - +125 c reflow peak temperature / time - - +260/10sec c parameter min. typ. max. units 1.8v supply voltage(vdl,cavdl,cpvdl0,cpvdl1) -0.3 - +2.1 v 3.3v supply voltage(lpvdh,lavdh) -0.3 - +4.0 v 1.8v cmos input voltage -0.3 - vdl+0.3 v 3.3v cmos input voltage -0.3 - lavdh+0.3 cmos output voltage -0.3 - +2.1 v cml receiver input voltage -0.3 - cavdl+0.3 v lvds transmitter output voltage -0.3 - lavdh+0.3 v output current -30 - 30 ma storage temperature -55 - +125 c junction temperature - - +125 c reflow peak temperature / time - - +260/10sec c maximum power dissipation @+25 - - 2 w lead temperature (soldering, 10sec) - - +260 c parameter min. typ. max. units 1.8v supply voltage vdl,cavdl,cpvdl,lpvdl 1.62 1.80 1.98 v 3.3v supply voltage(lavdh) 3.00 3.30 3.60 v operating temperature 0 - 70 parameter min. typ. max. units 1.8v supply voltage(vdl,cavdl,cpvdl0,cpvdl1) except for the 12 bit color depth mode 1.62 1.80 1.98 v 1.8v supply voltage(vdl,cavdl,cpvdl0,cpvdl1) for the 12 bit color depth mode 1.71 1.80 1.89 v 3.3v supply voltage(lpvdh,lavdh) 3.00 3.30 3.60 v operating temperature 0 - 70 13/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. electrical specifications 1.8v & 3.3v cmos dc specifications table 10. thcv215 and THCV216 1.8v & 3.3v cmos dc specifications cml & lvds dc specifications table 11. thcv215 cml & lvds dc specifications 7deoh 7+&9&0/ /9'6'&6shflilfdwlrqv symbol parameter conditions min. typ. max. units vih high level input voltage 0.65 vdl - vdl v vil low level input voltage 0 - 0.35 vdl v voh high level output voltage ioh=-2ma vdl-0.45 - - v vol low level output voltage iol=2ma - - 0.2 v iih input leak current high vin=vdl - - 10 ua iil input leak current low vin=0v - - 10 ua vih3 high level input voltage (3.3v inputs) 2.1 - lavdh v vil3 low level input voltage (3.3v inputs) 0 - 0.8 v voh3 high level output voltage (3.3v outputs) ioh=-4ma 2.4 - - v vol3 low level output voltage (3.3v outputs) iol=4ma - - 0.4 v iih3 input leak current high (3.3v inputs) vin=lavdh - - 10 ua iil3 input leak current low (3.3v inputs) vin=0v - - 10 ua symbol parameter conditions min. typ. max. units vtth lvds differential input high threshold - - 100 mv vttl lvds differential input low threshold -100 - - mv itih lvds input leak current high pdn=l, tlxn+/-=lavdh - - 10 ua itil lvds input leak current low tlxn+/-=0v,pdn=l - - 10 ua rtin lvds differential input resistance pdn=l 80 100 120 w vtod cml differential mode output voltage drv[1:0]=l,h pre[1:0]=l,l 200 300 400 mv pre[1:0]=l,l - 0 - % pre[1:0]=h,l 80 100 120 % pre[1:0]=l,l mv pre[1:0]=h,l mv itoh cml output leak current high pdn=l - 10 ua itos cml output short circuit current cavdl=1.8v -90 - - ma pre cml pre-emphasis level cavdl-vtod cavdl-2 vtod vtoc cml common mode output voltage symbol parameter conditions min. typ. max. units vrth cml differential input high threshold - - 50 mv vrtl cml differential input low threshold -50 - mv irih cml input leak current high pdn=l, rxn+/-=cavdl - - 10 ua iril cml input leak current low pdn=l,rxn+/-=0v - - 10 ua irrih cml input current high rxn+/-=cavdl - - 2 ma irril cml input current low rxn+/-=0v -6 - - ma rrin cml differential input resistance 80 100 120 w lvds differential mode output voltage (normal swing) rl=100, rs=h 250 350 450 mv lvds differential mode output voltage (reduced swing) rl=100, rs=l 100 200 300 mv vrod change in vrod between complementary output states rl=100 - - 35 mv vroc lvds common mode output voltage rl=100 1.125 1.25 1.375 v vroc change in vroc between complementary output states rl=100 - - 35 mv iros lvds output short circuit current rlxn+/-=0v -24 - - ma iroz lvds output tri-state current pdn=l, rlxn+/-=0v / lavdh x=a~f,clk, n=0, 1 - - 10 ua vrod 14/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. supply currents 7deoh 7+&96xsso\&xuuhqwv 7deoh 7+&96xsso\&xuuhqwv )ljxuh :ruvw&dvh3dwwhuq symbol parameter conditions min. typ. max. units itccw supply current for 1.8v power supply (worst case pattern) col[1:0]=h,h pre[1:0]=h,l sdsel=h - - 210 ma itccw33 supply current for 3.3v power supply (worst case pattern) col[1:0]=h,h pre[1:0]=h,l sdsel=h - - 90 ma itccs power down supply current pdn=l all inputs =fixed l or h - - 200 ua symbol parameter conditions min. typ. max. units irccw supply current for 1.8v power supply (worst case pattern) col[1:0]=h,h sdsel=h rs=h - - 160 ma irccw33 supply current for 3.3v power supply (worst case pattern) col[1:0]=h,h sdsel=h rs=h - - 190 ma irccs power down supply current pdn=l all inputs =fixed l or h - - 200 ua vdiff = (tlclkn +) - (tlclkn-) n=0,1 ttcip vdiff=0v next cycle current cycle previous cycle tlan +/- tlbn +/- tlcn +/- tldn +/- tlen +/- tlfn +/- control bit data enable h h 15/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. switching characteristics 7deoh '(uhtxluhphqw 7deoh 7+&96zlwfklqj&kdudfwhulvwlfv 7deoh 7+&96zlwfklqj&kdudfwhulvwlfv symbol parameter conditions min. typ. max. units tdeh de=high duration 2ttcip - - sec tdel de=low duration 2ttcip - - sec symbol parameter conditions min. typ. max. units col[1:0]=l,l | l,h 10 - 50 ns col[1:0]=h,l 11.76 - 50 ns col[1:0]=h,h 13.3 - 50 ns ttcih lvds differential clock high time 2 ttcip/7 - 5 ttcip/7 ns ttcil lvds differential clock low time 2 ttcip/7 - 5 ttcip/7 ns ttcip=75mhz -440 - 440 ps ttcip=85mhz -390 - 390 ps ttcip=100mhz -330 - 330 ps ttip1 lvds input data position0 -tsk 0 +tsk ns ttip0 lvds input data position1 ttcip/7-tsk ttcip/7 ttcip/7+tsk ns ttip6 lvds input data position2 2 ttcip/7-tsk 2 ttcip/7 2 ttcip/7+tsk ns ttip5 lvds input data position3 3 ttcip/7-tsk 3 ttcip/7 3 ttcip/7+tsk ns ttip4 lvds input data position4 4 ttcip/7-tsk 4 ttcip/7 4 ttcip/7+tsk ns ttip3 lvds input data position5 5 ttcip/7-tsk 5 ttcip/7 5 ttcip/7+tsk ns ttip2 lvds input data position6 6 ttcip/7-tsk 6 ttcip/7 6 ttcip/7+tsk ns ttisk lane0/1 lvds input clock skew -0.3 ttcip - 0.3 ttcip ns ttrf cml output rise and fall time(20%-80%) 50 - 150 ps ttosk cml lane0/1 output inter pair skew -2 - 2 ui ttcd input clock to output data delay (56/(5 n)+6.1) ttcip-5 (1) - (56/(5 n)+6.1) ttcip+5 (1) ns ttpd power on to pdn high delay 0 - - ns ttpll0 pdn high to cml output delay - - 10 ms ttpll1 pdn low to cml output high fix delay - - 20 ns ttnp0 lockn high to training pattern output delay - - 10 ms ttnp1 lockn low to data pattern output delay - - 10 ms (1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively. ttcip tsk tlclk period lvds receiver skew margin symbol parameter conditions min. typ. max. units col[1:0]=l,l | l,h 333 ttcip/30 1667 ps col[1:0]=h,l 294 ttcip/40 1250 ps col[1:0]=h,h 266 ttcip/50 1000 ps trisk cml lane0/1 input inter pair skew margin - - 15 ui trlvt lvds differential output transition time - 0.6 1.5 ns trop1 lvds output data position0 -0.25 0 0.25 ns trop0 lvds output data position1 ttcip/7-0.25 ttcip/7 ttcip/7+0.25 ns trop6 lvds output data position2 2 ttcip/7-0.25 2 ttcip/7 2 ttcip/7+0.25 ns trop5 lvds output data position3 3 ttcip/7-0.25 3 ttcip/7 3 ttcip/7+0.25 ns trop4 lvds output data position4 4 ttcip/7-0.25 4 ttcip/7 4 ttcip/7+0.25 ns trop3 lvds output data position5 5 ttcip/7-0.25 5 ttcip/7 5 ttcip/7+0.25 ns trop2 lvds output data position6 6 ttcip/7-0.25 6 ttcip/7 6 ttcip/7+0.25 ns trosk lane0/1 lvds output clock skew - - 50 ps trdc input data to output clock delay (178+68 n) trbit-5 (1) - (178+68 n) trbit+5 (1) ns trpd power on to pdn high delay 0 - - ns trhpd0 pdn high to htpdn low delay - - 1 us trhpd1 pdn low to htpdn high delay - - 1 us trpll0 training pattern input to lockn low delay - - 10 ms trpll1 pdn low to lockn high delay - - 10 us trlck0 lockn low to lvds output delay - - 1 ms trlck1 lockn high to lvds high-z delay - - 0 ns (1) n =3, 4, and 5 for 6/8bit, 10bit, and 12bit mode, respectively. unit interval trbit 16/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. ac timing diagrams and test circuits thcv215 lvds input switching characteristics figure 10. thcv215 lvds in put switching timing diagrams tlxn6 vdiff = (tlclkn +) - (tlclkn-) x=a,b,c,d,e,f n=0,1 tlxn5 tlxn4 tlxn3 tlxn2 tlxn1 tlxn0 tlxn6 tlxn5 tlxn4 tlxn3 tlxn2 tlxn1 vdiff = (tlxn +) - (tlxn-) ttcip vdiff=0v ttip1 ttip0 ttip6 ttip5 ttip4 ttip3 ttip2 vdiff = (tlclk0 +) - (tlclk0-) vdiff=0v vdiff = (tlclk1 +) - (tlclk1-) vdiff=0v ttisk ttcih ttcil 17/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. THCV216 lvds output switching characteristics figure 11. THCV216 lvds output switching timing diagrams )ljxuh7+&9/9'62xwsxw6zlwfklqj7lplqj'ldjudpdqg7hvw&lufxlw rlxn6 vdiff = (rlclkn +) - (rlclkn-) x=a,b,c,d,e,f n=0,1 rlxn5 rlxn4 rlxn3 rlxn2 rlxn1 rlxn0 rlxn6 rlxn5 rlxn4 rlxn3 rlxn2 rlxn1 vdiff = (rlxn +) - (rlxn-) trop1 trop0 trop6 trop5 trop4 trop3 trop2 ttcip vdiff=0v vdiff = (rlclk0 +) - (rlclk0-) vdiff=0v vdiff = (rlclk1 +) - (rlclk1-) vdiff=0v trosk rl=100 5pf 20% 80% rlxn+ rlxn- x=a,b,c,d,e,f n=0,1 vdiff = (rlxn +) - (rlxn-) trlvt trlvt 18/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. thcv2 15 cml o utput switchi ng characteristics figure 13. thcv215 cml output switching timing diagrams and test circuit THCV216 cml input switching characteristics figure 14. THCV216 cml input timing diagrams txn+ txn- n=0,1 75 200nf 75 200nf < 5mm 20% 80% vdiff = (txn +) - (txn-) ttrf ttrf vdiff = (tx0 +) - (tx0-) vdiff=0v vdiff = (tx1 +) - (tx1-) vdiff=0v ttosk 50 50 vdiff = (rx0 +) - (rx0-) vdiff = (rx1 +) - (rx1-) vdiff=0v vdiff=0v trisk 19/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. de period requirement figure 15. de period requirement latency characteristics figure 16. thcv215 and THCV216 latency vdiff = (tlclk0 +) - (tlclk0-) vdiff=0v ttcd vdiff = (tx0 +) - (tx0-) vdiff = (rx0 +) - (rx0-) vdiff=0v trdc pixel 1st bit pixel 1st bit vdiff = (rlclk0 +) - (rlclk0-) vdiff = (tlclk0+) C (tlclk0-) vdiff = (tlc0+) C (tlc0-) de de de de de de tdeh tdel 20/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. lock and unlock sequence figure 17. thcv215 lock/unlock sequence )ljxuh7+&9/rfn8qorfn6htxhqfh ttpd and trpd minimum is 0sec; therefore, pdn can be applied at the same time as vdd18 and vdd33. ttpll0 is the time from both pdn=high and htpdn=low moment to training pattern ignition. htpdn could transit from high to low under pdn=high condition at thcv215, which is different from what figure 17 indicates but is natural situation. vdd18 : 1.8 v power supply vdd 33 : 3.3 v power supply vdd 18 : 1.8v power supply vdd33 : 3.3v power supply power on vdd18 vdd33 tlclkn htpdn pdn lockn fix to vdd18 cdr training pattern aln training pattern cdr training pattern ttpll0 ttnp1 ttnp0 ttpll1 txn lvds data pattern tlxn+/- 1.5v ttpd x=a,b,c,d,e,f n=0,1 normal pattern low-level lvds clock pattern normal pattern rxn power on vdd18 vdd33 htpdn pdn lockn cdr training pattern trhpd0 trpll0 trhpd1 rlx high-z trlck0 trlck1 1.5v trpd high-z lvds data pattern rlclk x=a,b,c,d,e,f n=0,1 aln training pattern normal pattern trpll1 lvds clock pattern 21/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. note 1 )htpdn/lockn connection between high vdd v- by -one ? hs transmitter and THCV216 when using THCV216 with high vdd v-by-one ? hs transmitter, user have to take care of htpdn/lockn connection because THCV216 htpdn/lockn output pins absolute maximum ratings are vdl+0.3v; therefore high vdd pull-up at transmitter side can cause violation of usage. users are supposed to connect those htpdn/lockn line between two devices with appropriate level-shifter configuration. 2 )lvds input pin connection when lvds line is not drove from the previous device, the line is pulled up to 3.3v internally in th cv215.this can cause violation of absolute maximum ratings to the previous lvds tx device whose operating condition is lower voltage power supply than 3.3v. this phenomenon may happen at power on phase of the whole system including thcv215. one solution for this problem is pd=l control during no lvds input period because pull-up resistors are cut off at power down state. 3 )power on sequence dont input tclk#+/- before power supply to th cv215 is on in order to keep absolute maximum ratings. 4 )unused lvds input pins first, select appropriate color depth with col0,col1 pins. if there are inevitably remained lvds no input pins which are originally active, tie them to gnd. second, avoid the situation that lvds input pins in use are open. you can use pdn=l control during no lvds input period to cut off pulled-up resistors. 5 )cable connection and disconnection dont connect and disconnect cml and lvds cables, when the power is supplied to the system. 6 )gnd connection connect the each gnd of the pcb which transmitter, receiver and th cv215 on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. lavdh lvds input buffer internal circuit of thcv 215 low vdd lvds tx thcv 215 or lvds tx integrated device lvds tx side pcb lvds rx side pcb lockn htpdn THCV216 1.8v 10k mosfet (vth<1.2v) 1.8v 10k mosfet (vth<1.2v) 3.3v 3.3v 10k 10k v-by-one ? hs transmitter (ex. thcv217,thcv233) 1.8v tolerant transistor v-by-one ? hs tx side pcb v-by-one ? hs rx side pcb d s g d s g 22/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. 7 )multi drop connection multi drop connection is not recommended. 8 )multiple counterpart use multiple counterpart use such as following system is not recommended. p.1 5 ttisk spec should be kept. asynchronous use such as following system is not recommended. 9 )multiple device connection htpdn and lockn signals are supposed to be connected proper for their purpose like the following figure. htpdn should be from just one rx to multiple tx because its purpose is only ignition of all tx. lockn should be connected so as to indicate that all rx cdr become ready to receive normal operation data. lockn of tx side can be simply split to multiple tx. there can be other applicable circuits like or gate of lockn, npn transistor with resistors as inverter, etc. also possible time difference of internal processing time (p.15 thcv215 ttcd and THCV216 trdc ) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple THCV216, which may have internal fifo. lvds rx lvds rx ic clk data data thcv 216 r l clk 0 - r l clk 0+ r l clk 1 - r l clk 1+ lvds tx lvds tx ic clk clk data data thcv 215 t l clk0 - t l clk 0+ t l clk 1 - t l clk 1+ lvds rx thcv 216 lvds rx r l clk 0,1 - r l clk 0,1+ thcv215 htpdn lockn thcv215 htpdn lockn THCV216 htpdn lockn pdn THCV216 htpdn lockn pdn source device destination device ex. synchronized time diff. comes up clkin.1 clkin.2 clkout.1 clkout.2 internal processing time ttcd internal processing time trdc fifo fifo 23/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)201 6 thine electronics, inc. package 64 lead molded thin shrink small outline package, jedec figure 19. 64 pin tssop package physical dimension 0. 50 nom 0.17~0.27 17. 00 0.10 1 0. 25 nom 0. 60 0.15 1. 00 nom 0. 10 0.05 0. 90 0.10 1. 20 max detail of lead end unit:mm 0.10 0~8 8.10 0.20 6.10 0.10 64 24/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)20 1 6 thine electronics, inc. notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. this product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine electronics, inc. (thine) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product. except where mandated by applicable law or deemed necessary by thine based on the users request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damage may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. 25/26
thine electronics, inc. security e thcv215-216_rev.2.70_e copyright(c)20 1 6 thine electronics, inc. 26/26

▲Up To Search▲

Price & Availability of THCV216

	To Download THCV216 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .